VHDL Simulation Extends The Range Of Powerful Test Programming Tools

Recognising that this process needs to be as easy and as fast as possible, Diagnosys has introduced support for VHDL logic simulation.

Describing the functionality of a device using the Verilog Hardware Description Language (IEEE 1364) allows a behavioural model of a device to be created. This model can then be configured into a Testbench which allows input stimulus to be applied and output responses from the model to be determined. Using these input and output patterns a functional test routine for a device is automatically created by TestVue software.

Similarly, building a software model of a PCB using behavioural models and then simulating using a Testbench allows a board level test program to be created.

By supporting the common VHDL standards, Diagnosys has provided another powerful and flexible programming tool for users of its systems to help in the creation of test programs.

VHDL simulation support is available in TestVue software which is used across the PinPoint range of products.